1. Field of the Invention
The present invention relates to the field of integrated circuits, and more specifically to an inductance formed on a semiconductor substrate.
2. Discussion of the Related Art
FIG. 1 shows, in a very simplified perspective view, a first example of a conventional inductance 1 formed on a semiconductor substrate 2. Inductance 1 includes a number of generally concentric turns or spirals obtained by the deposition of a conductive element on an insulating layer (dielectric 3). The number of turns may also be smaller than 1. Insulating layer 3, for example silicon oxide, rests on semiconductor substrate 2, or on the penultimate metallization level (not shown) added on this substrate after forming of the other components, which are integrated (for example, transistors and the like). Substrate 2 is assumed to be grounded by its lower surface, to simplify the discussion.
FIG. 2 shows the equivalent electric diagram of inductance 1 of FIG. 1. Inductance 1 is symbolized in the form of a perfect inductance L in series with a resistor Rs between two terminals 5 and 6 corresponding to the ends of the winding of FIG. 1. Dielectric 3 forms stray capacitances C between the inductance and the substrate. Further, substrate 2 is resistive and it exhibits resistors R between its upper and lower surfaces. Resistors R ground each electrode of a capacitor C opposite to inductance L.
A disadvantage of an inductance such as illustrated in FIG. 1 is its high losses. When the inductance conducts a variable current, these losses occur via resistor Rs, capacitors C, and resistors R, and have the disadvantage of strongly decreasing the quality factor of the inductance. This quality factor depends on the resistive losses, that is, on series resistance Rs and on the resistance brought by the substrate to the ground connection.
A first solution to increase the quality factor of the inductance is to minimize its series resistance Rs. For this purpose, the width of the conductive track constituting of planar inductance 1 has to be increased. This results in increasing the value of the stray capacitances of dielectric 3 and, accordingly, the resistive losses in the substrate. A compromise thus has to be made according to the operating frequency for which the inductance is intended.
Another known solution to increase the quality factor is described in European patent application EP-A-0,780,853, which is incorporated herein by reference. An inductance structure on a silicon substrate including a conductive plane located between the inductance and the substrate is provided therein. This conductive plane, isolated from the substrate and from the inductance, is connected to ground or to a cold point of the circuit, to establish a xe2x80x9cshieldingxe2x80x9d or xe2x80x9celectrostatic screenxe2x80x9d between the inductance and the semiconductor substrate. To avoid dissipation by creation of eddy currents in the conductive plane, said application provides a cutting-up of this conductive plane.
A type of inductance with a conductive plane cut-up according to an example of the above-mentioned application is illustrated in FIG. 3.
FIG. 3 shows, in a simplified perspective view, an inductance 1 formed, as previously, of one or several coplanar spirals made of a conductive material. Inductance 1 is separated from a conductive plane 7 by an insulating layer 8. Conductive plane 7 is itself deposited on an insulating layer (dielectric 3) resting on substrate 2 or on a metallization level. Conductive plane 7 is cut up in longitudinal strips 9 connected to a lateral strip 10. In the example illustrated in FIG. 3, longitudinal strips 9 are located on either side of inductance 1 by being connected to lateral end strips of conductive plane 7. The remaining conductive elements of plane 7 are grounded. The effect due to eddy currents is thus strongly decreased, but the structure of FIG. 3 has disadvantages.
A first disadvantage is that, for a general insulator thickness above substrate 2, the dielectric thickness available between the inductance and the conductive plane is reduced with respect to the case of FIG. 1.
Indeed, the conductive plane is:
either a metal layer or a polysilicon layer interposed between the inductance and the substrate, and thus reducing the dielectric thickness and increasing the stray capacitances between the inductance and the substrate or between the inductance and the conductive layer if said layer is grounded;
or a very heavily-doped layer, diffused in the silicon and the forming of which requires a dielectric etching (thick oxide (LOCOS) separating the active components from one another), and thus, in the end, a smaller dielectric thickness between the inductance and this diffused layer.
This results in an increase in the stray capacitances between the inductance and the ground while it is generally desired to minimize the value of the stray capacitance.
Another disadvantage of the structure provided in FIG. 3 is that, when inductance 1 is run through by a variable current, an electromotive force due to the inductive coupling existing between the strips and the inductance appears in each of strips 9. Similarly, an electromotive force due to the inductive coupling between lateral strip 10 and inductance 1 appears in this lateral strip. These electromotive forces cause losses. Indeed, each of the points of strips 9 and 10 is at a non-zero voltage with respect to the ground due to the induced electromotive forces and, thereby, losses occur via a capacitance due to layer 8 behaving as a dielectric and the ohmic resistance of the substrate. These ohmic capacitances and resistances are distributed variables, different at each point of conductive plane 7.
All these losses make the behavior of the structure of FIG. 3 unsatisfactory and lower quality factor Q of the inductance.
It should be noted that, for the solution provided by the above-mentioned European patent application to provide a result, the strips of the conductive plane needs to be, for the most part, located under the conductive track forming inductance 1.
The above-mentioned patent application provides other ways of cutting up the conductive plane (see FIGS. 7, 9, and 12 of this application). However, in all the provided examples of said application, the inductance is, for the most part, on conductive strips and there remain conductive plane portions in which a high induced electromotive force causes the undesirable effect which has been described.
The present invention aims at providing a novel integrated circuit inductance structure which overcomes the disadvantages of known structures.
The present invention more specifically aims at providing a solution which combines the advantages of a low stray capacitance and of a low ground access ohmic resistance.
The present invention also aims at providing a solution which reduces or minimizes the losses linked to the inductance operation and, in particular, which reduces or minimizes possible induced electromotive forces.
To achieve these objects as well as others, the present invention provides an integrated circuit inductance structure, including a silicon substrate, at least one planar winding of a conductive track, a resistive layer, not etched under the winding, a dielectric layer between the winding and said resistive layer, and discontinuous conductive sections, individually parallel to a portion of the winding which is the closest and electrically connected to ground and to said resistive layer.
According to an embodiment of the present invention, said conductive sections are, for the most part, not arranged under projections of the winding.
According to an embodiment of the present invention, each conductive section is placed as close as possible to the closest winding portion.
According to an embodiment of the present invention, each portion of the winding is associated, along its length, to several conductive sections.
According to an embodiment of the present invention, said conductive sections are connected to a contact point by several conductive tracks, each of the conductive tracks being arranged so that the resultant of the electromotive forces induced by the inductance is substantially null.
According to an embodiment of the present invention, each of the conductive tracks substantially is an axis of symmetry of the inductance.
According to an embodiment of the present invention, said conductive sections are formed in a same metallic level as the track forming an inductance.
According to an embodiment of the present invention, said resistive layer has a doping level ranging between 1016 and 1019 atoms/cm3, preferably, on the order of 1017 atoms/cm3.